1. Field of the Invention
The invention relates to a memory programming method, and more particularly to a memory programming method for a NAND flash memory.
2. Description of the Related Art
A NAND flash is a memory proposed by Toshiba. NAND Flash is a non-volatile memory, thus maintaining data storage without power supply. Moreover, NAND flash has speedy programming time and erasing time. In a NAND flash, each storage cell occupies a relatively small chip area. Thus, a NAND flash has larger storage density than other memories.
In general, a NAND flash may be grouped into single level cells and multi level cells, wherein the multi level cell may store more than one bit per cell (such as ‘00’, ‘01’, ‘10’ and ‘ 11’), thus having larger storage density than the single level cell.
FIG. 1A to FIG. 1C show the distribution diagrams of a threshold voltage when a multi level cell (MLC) is programmed, wherein the multi level cell is used to store a two-bit data. A most significant bit (MSB) and a least significant bit (LSB) of the two-bit data correspond to different pages, i.e. different addresses. For example, the least significant bit corresponds to a first page and the most significant bit corresponds to a second page, wherein an address of the first page (lower page) is lower than that of the second page (upper page) in the NAND flash. In addition, a logic state ‘11’ of the two-bit data corresponds to an erased state of the multi level cell, wherein the erased state may also be an initial state for performing a programming operation.
FIG. 1A shows a distribution diagram of a threshold voltage Vth during a first page (i.e. a lower page) programming operation of a conventional multi level cell. After the first page programming operation is completed, a two-bit data stored in the multi level cell may be a logic state ‘11’ or ‘10’. Referring to FIG. 1A, the arrow A indicates that the multi level cell is programmed from the logic state ‘11’ to the logic state ‘10’, wherein the logic state ‘11’ and the logic state ‘10’ correspond to different threshold voltage ranges, respectively. Next, the first page programming operations of the multi level cells in the other adjacent bit lines are performed. FIG. 1B shows a distribution diagram of the threshold voltage Vth during a second page (i.e. an upper page) programming operation of the multi level cell described in FIG. 1A. As shown in FIG. 1B, the arrow B indicates that the multi level cell is programmed from the logic state ‘11’ to the logic state ‘01’, and the arrow C indicates that the multi level cell is programmed from the logic state ‘10’ to the logic state ‘00’. Next, the second page programming operations of multi level cells in the other adjacent bit lines are performed. FIG. 1C shows a threshold voltage offset of the multi level cell shown in FIG. 1B caused by a coupling effect. As shown in FIG. 1C, if the two-bit data is in the logic state ‘01’ and ‘00’, an offset Voffset1 between the practical threshold voltage range and the ideal threshold voltage range of the multi level cell exists due to the interferences caused by the second page programming operations of the other adjacent multi level cells and the coupling effect of the floating gates. Moreover, if the two-bit data is in the logic state ‘10’, an offset Voffset2 between the practical threshold voltage range and the ideal threshold voltage range of the multi level cell exists due to the interferences caused by the first and second page programming operations of the other adjacent multi level cells and the coupling effect of the floating gates. The threshold voltage range of the programming operation (between a maximum threshold voltage Vmax and a minimum threshold voltage Vmin) is increased when the offset value of the threshold voltage is increased.
Therefore, it is desired that a memory programming method be provided, which can decrease the offset of the threshold.